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careers@nuvacore.aiCPU Custom Library Cell design
Full-time · US (Santa Clara, CA / Austin, TX) · IC
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.
CPU Custom Library Cell design
As a Custom Library Circuit Engineer, you will participate in the following :
- Design and characterize library cells including flip-flops, clock-gating cells, level shifters, and special purpose aoi cells to optimize PPA at advanced process nodes.
- Own end-to-end library IP closure: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization
- Partner with Foundry/PDK, CAD, Physical Design, and DFT teams to benchmark new process technology, validate IP on testchips, and co-optimize cells for downstream design PPA.
- Define and drive adoption of Tools, Flows, and Methodology — including characterization automation and compiler QA — to raise design efficiency and set team-wide best practices.
MINIMUM QUALIFICATIONS
- Hold a BS or MS degree with (ideally) 12+ years of experience in standard cell and/or custom memory circuit design.
- Hands-on transistor-level design experience with static circuits and state-retaining elements (latches, flops), as well as custom logic gates at advanced CMOS nodes.
- Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom cell and memory design workflows.
- Experience providing feedback to foundry partners to help improve PPA, yield, and other important qualities in future revisions of the PDK.
- Well-versed in STA and Liberty/CCS model correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.
- Strong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.
REQUIREMENTS — PREFERRED
- Experience across the full design flow of a custom circuit— cell/memory architecture, circuit design, compiler automation, characterization, and timing/model generation.
- Experience translating PDK device characteristics into circuit decisions.
- Proven PPA-focused execution for standard cells, including architecture trade-offs, critical-path modeling, full-cut analysis, and Monte Carlo variation studies.
- Experience using Agentic AI tools for productivity and automation.