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careers@nuvacore.aiCPU Memory Subsystem Verification Engineer
Full-time · Multiple Levels · US / Canada / India
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the correctness of the Nuvacore CPU's memory subsystem. As part of the design verification (DV) team, you will help verify the load-store unit, memory management units (MMU), and bus interface units — building the test plans, environments, and checkers that find deep bugs in memory ordering and address translation long before silicon, working shoulder-to-shoulder with architecture and RTL design.
THE ROLE
- Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU memory subsystem — load-store, memory management units (MMU/TLBs), and bus interface units — including the memory-consistency and ordering rules.
- Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, checkers, transactors, and coverage — that exercise load/store paths, address translation, and bus transactions end to end.
- Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as ordering, hazards, aliasing, TLB maintenance, and fault handling.
- Performance Verification: Partner with architects to correlate RTL against performance models, hunting latency, bandwidth, and ordering-related stall issues.
- Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
- Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.
REQUIREMENTS — MUST HAVE
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
- 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
- Strong knowledge of CPU micro-architecture and the memory subsystem (load-store, MMU/TLBs, bus interfaces), including a good understanding of memory-consistency and ordering rules.
- Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.
- Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
- Experience writing and debugging tests in assembly for CPU verification.
REQUIREMENTS — nice to HAVE
- Memory-subsystem verification — load-store, MMU/TLBs, page-table walks, or bus interface units.
- Verifying memory-consistency models and ordering — fences, barriers, and atomics.
- Random instruction sequence (RIS) stimulus generation.
- Constrained-random verification and coverage-driven closure.
- Assertions and formal verification.
- Emulation/FPGA and silicon bring-up and debug (waveforms, trace).