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careers@nuvacore.aiDebug Sub-System Verification Engineer
Full-time · Multiple Levels · US / Canada / India
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the correctness of the Nuvacore CPU's debug infrastructure. As part of the design verification (DV) team, you will help verify the design-for-debug features — hardware trace, debug access, breakpoints, and special-purpose registers — building the test plans, environments, and checkers that find deep bugs long before silicon, and standing up the debug features the whole project relies on during bring-up.
THE ROLE
- Plan & Strategy: Drive the verification scope, strategy, and test plans for the design-for-debug features — hardware trace, debug access, breakpoints, resets, and special-purpose registers.
- Environment Setup: Build, maintain, and scale robust verification environments — stimulus, checkers, transactors, and coverage — that exercise trace, debug access, and breakpoints end to end.
- Test & Debug: Generate directed and random tests in assembly, C, or scripts to drive debug scenarios across simulation and emulation.
- Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
- Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support post-silicon debug bring-up using trace and waveform tools.
REQUIREMENTS — MUST HAVE
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
- 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
- Strong knowledge of CPU micro-architecture and processor debug features — hardware trace, debug access, and special-purpose registers — with an understanding of debug in a modern architecture (x86, ARM, or RISC-V).
- Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.
- Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
- Experience writing and debugging tests in assembly for CPU verification.
REQUIREMENTS — nice to HAVE
- Processor debug and hardware-trace verification.
- Debug access ports and on-chip debug/trace architecture.
- Post-silicon debug and trace tools.
- Constrained-random verification and coverage-driven closure.
- Assertions and formal verification.
- Emulation/FPGA and silicon bring-up and debug (waveforms, trace).