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careers@nuvacore.aiSignal Integrity and Power Integrity Engineer
WHAT YOU’LL OWN
- End-to-End SI Design & Modeling:Support System Signal Integrity (SI) design on data center hardware products by designing, simulating, and validating high-performance interconnect solutions across chips, advanced packaging, and PCBs. Perform pre- and post-route channel modeling, simulation, and electromagnetic analysis on high-speed I/Os, IC packages, and complex 3D structures.
- Power Integrity (PI) & System Analysis:Model and analyze complex AC/DC power delivery networks (PDN) , addressing core signal integrity, power integrity, clocking, and simultaneous switching noise (SSN) challenges across system-level interconnections.
- Documentation & DFM Integration:Author detailed layout guidelines, test plans, test reports, and SI/PI documentation. Define optimal package and PCB materials and layer stack-ups while collaborating with fabrication vendors to resolve Design for Manufacturability (DFM) constraints.
- Cross-Functional & Vendor Collaboration:Partner closely with chip, board, layout, and system engineers, alongside internal functional teams (HW design, eCAD, Mechanical, Power, EMC, Diagnostics). Collaborate directly with ASIC, package, connector, and cable vendors to explore design trade-offs and engineer new interconnect technologies.
- Hardware Validation & Bring-Up:Support product and prototype bring-up, customer engagements, qualification, validation, and laboratory troubleshooting. Partner with test engineers to configure chips and ensure robust system operational margins.
- Methodology & Technology Roadmap:Drive state-of-the-art signal/power integrity analysis methodologies and deliver technical leadership to influence long-term technology roadmaps across next-generation interconnects, advanced packaging, and cross-functional system co-design.
REQUIREMENTS — MUST HAVE
- Education & Experience:Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or a related field with 6+ years of relevant experience, OR a Master’s degree with 3+ years of relevant experience.
- SI/PI Theory & Core Fundamentals:Deep knowledge of transmission line theory, electromagnetic (EM) theory, coupling mechanisms, and EE fundamentals related to signal and power integrity analysis.
- High-Speed Interfaces:Experience in DDR / LPDDR and High-Speed IO (such as PCIe Gen 5/6/7, USB/USB-C, UCIE etc.) modeling and simulation
- Channel Simulation & Behavioral Modeling:Expertise in end-to-end channel modeling and link budget analysis using time-domain and statistical simulation methodologies. Understanding of behavioral I/O models (IBIS, IBIS-AMI) and transceiver equalization techniques (CTLE, DFE, TX equalization).
- PDN:Experience in PDN modeling and simulation, with experience in PMIC design and modeling. Good understanding of how die/package/board decoupling impacts power supply noise across different frequency ranges.
- Lab Validation & Measurement:Hands-on experience in a laboratory environment configuring, interpreting, and analyzing high-speed measurements using VNAs, TDRs, and oscilloscopes.
REQUIREMENTS — nice to HAVE
- Advanced Degree & Tenure:Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field with 8+ years of relevant industry experience.
- Technical Leadership & Production Lifecycle:3+ year of formal or informal experience in technical leadership. Experience driving the product development process through mass-volume production, managing layout, material, and manufacturing tradeoffs.
- Advanced Technology & Standards:Deep familiarity with data center standards (PCIe, DDR/LPDDR, SATA, Ethernet), advanced packaging design (including large body-size electronic packages), and optical transceiver module form factors and requirements.
- Advanced Tools & Signaling Expertise:Hands-on experience with PowerSI, 3D modeling tools such as ANSYS HFSS/Q3D, 2.5D tools such as ANSYS SIwave (or similar). Knowledge of on-chip power analysis flow (e.g., PTPX, Redhawk, Voltus), SoC physical design.