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careers@nuvacore.aiCPU Stimulus Development Engineer
Full-time · Multiple Levels · US / Canada / India
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking CPU Stimulus Development Engineers at multiple levels — from Senior Engineer to Principal level — to help build the stimulus that stresses the Nuvacore CPU. As part of the design verification (DV) team, you will develop the test generators and scenarios — from pseudo-random instruction streams that hammer micro-architectural corner cases to system-level scenarios like boot and power management — that drive coverage and expose deep bugs. The same stimulus is used across simulation, emulation, FPGA, and post-silicon, so you build it to run everywhere — working shoulder-to-shoulder with architecture, design, and the wider verification team.
THE ROLE
- Generators & Methodology: Design, develop, and scale the stimulus generators and their methodology — pseudo-random instruction generators and directed stimulus — that stress the functional and performance boundaries of the CPU.
- System-Level Scenarios: Build system-level scenarios — including boot, power management, and other full-system flows — alongside the instruction-level stimulus.
- Advanced Coverage: Extend the generators to cover advanced behaviors — vector processing, memory translation (MMU), cache coherence, interrupts, and out-of-order execution.
- Coverage Closure: Drive coverage closure — track coverage and improve the generation algorithms so the stimulus reaches the hard-to-hit corners.
- Failure Triage: Analyze simulation logs, root-cause issues, and resolve architectural and micro-architectural bugs with the design team.
- Pre/Post-Silicon Scaling: Scale the stimulus across simulation, emulation, FPGA, and silicon bring-up.
REQUIREMENTS — MUST HAVE
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
- 15+ years (Principal) or 4+ years (Senior Engineer) of experience in CPU design verification, test generation, or CPU validation.
- Experience building random-instruction and/or directed test generators for CPUs.
- Strong knowledge of CPU micro-architecture — ISA behavior, privileged architecture, and out-of-order execution — with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).
- Proficiency in C/C++/Rust and Python, plus assembly, for building generators and stimulus.
- Constrained-random and coverage-driven verification methodologies.
REQUIREMENTS — nice to HAVE
- Building generators that scale across a large CPU verification program.
- ISA certification / compliance workflows and test content.
- Micro-architectural corner-case targeting — coherence, MMU, branch prediction, or exceptions.
- Vector / SIMD stimulus generation.
- Emulation/FPGA and post-silicon validation scaling.
- Leading or mentoring a small stimulus or verification team.