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careers@nuvacore.aiVerification and Assertion IP Development Engineer
Full-time · Multiple Levels · US / Canada / India
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification and Assertion IP Development Engineers at multiple levels — from Senior Engineer to Principal level — to build the reusable verification and assertion IP that the whole team depends on. As part of the design verification (DV) team, you will develop the VIPs, models, transactors, and assertions that model the rest of the system around the design under test — driving protocol checking, coherency and deadlock stress, and system-level scenarios — so testbenches are reusable, thorough, and ready long before silicon.
THE ROLE
- Verification IP (VIP): Develop reusable transactors, models, and checkers that the DV team uses to build testbenches.
- Assertion IP (AIP): Develop assertions and checkers that model expected behavior and enable early bug hunting and formal property checking.
- System Modeling: Model the rest of the system around the design under test — device and behavioral models, including randomization of responses — so testbenches exercise realistic system behavior.
- Software & Performance Enablement: Model devices and behaviors so testbenches can also serve software bring-up and performance verification, not just functional verification.
- Stress Testing: Design VIPs to stress-test the design — coherency, deadlocks, and system-level scenarios such as power management and boot.
- Cross-functional Collaboration: Partner with RTL designers, architects, and the wider DV team to integrate VIPs, define coverage, and root-cause bugs.
REQUIREMENTS — MUST HAVE
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
- 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally building verification IP or reusable verification infrastructure.
- Strong experience building reusable verification components — transactors, models, and checkers.
- Strong experience with assertions and assertion-based or formal property checking.
- Strong Verilog/SystemVerilog, including synthesizable design — Nuvacore's VIPs are synthesizable — plus C/C++/Rust for models and reference behavior and a scripting language (Python).
- Strong knowledge of CPU and system micro-architecture — coherency and ordering — and familiarity with fabrics and interconnect protocols (e.g. AMBA, CHI, TileLink).
REQUIREMENTS — nice to HAVE
- Modeling devices and system behavior — randomized responses and error injection.
- Coherency and deadlock stress verification.
- System-level scenarios — power management, boot, and full-system flows.
- Enabling testbenches for software bring-up or performance verification.
- Formal property checking and assertion IP.
- Reuse across simulation, emulation, and FPGA.