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careers@nuvacore.aiCPU DFT Engineer
Full-time · Austin / San Jose / Markham · IC
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related pre-silicon and post-silicon activities. We will be delivering a DFT architecture which aligns with the projects industry leading power, performance, and area.
THE ROLE
As a CPU DFT Engineer, you will participate in the following areas:
- Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
- Develop scan and BIST insertion flows, implement DFT registers in design blocks
- Completing DFT architecture specifications
- Review and integrate third party IPs into DFT architecture
- Define verification plans for DFT features
- Review DFT coverage for scan and MBIST
- Verification of DFT features in RTL and gates, and power aware simulations
- Generate test content for silicon bringup, and support silicon bringup activities including yield analysis
REQUIREMENTS — MUST HAVE
- BS or MS with 7 years experience in DFT or DFT verification
- Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
- For scan role, able to define scan insertion, scan compression, and clking requirements, and define intest and extest modes
- For MBIST role, be very familiar with memory repair, and repair interaction with functional operation
- Strong understanding of JTAG, IEEE 1500 and IEEE 1687
- Experience with Verilog RTL and gate level netlists, including running and debugging simulations
- Strong communication skills and ability to work with cross functional teams
REQUIREMENTS — nice to HAVE
- Using DFT features to support system debug
- Leveraging AI tools to accelerate DFT work flows
- Porting test content and supporting silicon bringup on ATE platforms
- Experience in perl, python, or TCL