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careers@nuvacore.aiIC Package Engineer
WHAT YOU’LL OWN
- Architecture & Strategy: Lead research, development, and selection of advanced package architectures for AI accelerators, data center products, and next-generation product configurations. Define reference architectures for high-power, high-bandwidth multi-chiplet systems, emphasizing concept development, System-Technology Co-Optimization (STCO) modeling, and technology selection.
- Physical Design & Layout: Own and implement the physical design, layout, optimization, Design
- Verification (DV), and tape-out of packages, SiP (System-in-Package), and modules for advanced SoCs. Partner with internal teams to optimize chip floorplans, bump placements, and package sizes.
- Multi-Functional Leadership: Act as a collaborative leader working multi-functionally with silicon, SI/PI, thermal, mechanical, reliability, platform, product development, and vendor teams to achieve optimal electrical, thermal, and mechanical performance. Strategy includes optimizing package pin-outs and alignment of technology/product roadmaps.
- Advanced Technology Integration: Lead the architecture definition of sophisticated packaging solutions, including 2.5D/3D Interposers, Co-Packaged Optics (CPO), Integrated Voltage Regulators (IVR), and High-Speed IO (HSIO). Maintain a deep understanding of industry trends, metrology, characterization, and component validation.
- Flow Automation & Methodology: Define, explore, and develop design verification strategies, automated scripting workflows (e.g., Python), and new CAD tools to strengthen, streamline, and improve the efficiency of package design and release flows. Drive innovations and bug resolution directly with vendors and developers.
REQUIREMENTS — MUST HAVE
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Material Science, or a related technical field.
- 5+ years of experience in System/Package Design, Packaging Architecture, or Technology Engineering.
- Proficiency in Cadence APD (Advanced Package Designer) & SiP tools.
- Basic knowledge of high-speed IO interfaces, electromagnetic fields, IC packaging structures, and chip-package-board interactions.
- Basic knowledge of electronic packaging processes, manufacturing rules, and typical failure modes.
REQUIREMENTS — nice to HAVE
- Master's degree or Ph.D. in Electrical Engineering, Mechanical Engineering, Material Science, or a related field.
- 8 to 10+ years of comprehensive experience in packaging architecture, design, metrology, characterization, and component validation.
- Proven fundamentals across electrical, material, thermal, and mechanical engineering fields.
- Familiarity with advanced wafer-level processes, package assembly processes, substrate manufacturing technology, and advanced configurations (Flip Chip BGA, 2.5D/3D Interposer, CPO, etc.).
- Expertise in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP) and layout verification tools like Calibre.
- Solid understanding of Signal Integrity / Power Integrity (SI/PI) tools (XtractIM, PowerSI, HFSS, Q3D), package model extraction, S-parameters, and RLGC models.
- Proven understanding of high-speed interfaces (DDR, PCIe, UCIE) and high-speed layout constraints (crosstalk mitigation, differential pairs).
- Solid understanding of Design Rules Check (DRC), Design for Manufacturing (DFM), data collection/analysis, and statistical methods.
- Proficiency in scripting languages such as Python for design automation and flow efficiency improvements.