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careers@nuvacore.aiSoC Performance Modeling (Lead & ICs)
Full-time · US / Canada / UK / India or Hybrid · ICs / Lead
Nuvacore is building ground-up SoC silicon for next-generation compute workloads. As our SoC Performance Modeling Lead, you will design and own the performance and power models for the fabric NoC, DRAM controller, and IO blocks — correlating against RTL, prototyping ideas, and driving those improvements all the way to productization in future SoC designs.
THE ROLE
- Design, develop and own Nuvacore’s SoC-level performance and power models covering interconnect NoCs, distributed system caches, DRAM controllers, and IO controllers (PCIe / CXL).
- Identify ideas for improving the SoC’s performance and power characteristics; prototype and thoroughly characterize each idea in the model before driving productization with architects and RTL developers.
- Lead SoC-level PPA trade-off studies across CPU, memory subsystem, and interconnect — providing data-driven architectural guidance from pathfinding through tape-out.
- Perform detailed workload characterization to identify system-level bottlenecks and propose architectural solutions; collaborate with design, verification, and physical design teams on implementation.
- Drive model-to-RTL and model-to-silicon correlation; own debug and resolution of performance and power miscorrelation across pre- and post-silicon environments.
- Mentor engineers across the performance team; provide technical leadership on SoC modeling methodology, simulation infrastructure, and analysis tooling.
- Contribute to IP development through patents and, where applicable, external publication.
WHAT YOU'LL OWN
- SoC performance & power model: End-to-end model covering NoC fabric, DRAM controller, system caches, and IO — calibrated against RTL and silicon.
- Workload characterization: Benchmark analysis (SPEC, GeekBench, AI/ML inference, cloud, client traces) mapped to system-level bottlenecks.
- Feature productization: Prototype → characterize → productize pipeline for performance and power improvements across the SoC.
- Cross-team alignment: Architecture-to-implementation bridge across CPU, interconnect, memory, and system software teams.
REQUIREMENTS — MUST HAVE
- MS in Computer Architecture, Computer Engineering, Electrical Engineering, or related field (PhD preferred).
- 20+ years (Lead) or 8+ years (ICs) in SoC or ASIC architecture and/or performance engineering.
- 20+ years (Lead) or 8+ years (ICs) of hands-on experience building and validating SoC-level performance and power models using custom C++ model development.
- Deep expertise in at least one of: interconnect NoC design, DRAM controller architecture, distributed caches, coherency flows, or IO (PCIe / CXL).
- Demonstrable track record of productizing features that improve performance and power characteristics of a shipping SoC design.
- Strong C++ and Python / Perl skills; proficiency in RTL simulation environments and IP/SoC-level model-to-RTL correlation.
- Experience in RISC-V or ARM64 or x86 ISA and their system-level interactions.
- Familiarity with cache coherence protocols (MESI, MOESI, AMBA CHI) and scalable interconnect design.
REQUIREMENTS — nice to HAVE
- Published work or filed patents in SoC performance, power modeling, or interconnect architecture.
- Prior principal-level role at a SoC or ASIC design organisation.